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• Isplever Classic Tutorial
• Lattice Isplever Tutorial
• Isplever Classic Tutorial

IspLever Classic Project Navigator – used to create a new project, write a Verilog module, synthesize it, and create a JED file Dataman – used to program the created JED file onto an IC (GAL22V10 for Lab6). Meminitebr.mem bootloader file in the ispLEVER. The file meminitebr.mem is the compiled file. It is the program bootloader which will be placed in the XP2 EBR non volatile memory. For the bootloader reference guide, refer section Tutorial: Running ERIKA on Mico32 and FPG-EYE. Be sure that the file is present in the ispLever project directory. Free isplever classic 1.5 download. Development Tools downloads - ispLEVER Classic by Lattice Semiconductor Corporation and many more programs are available for instant and free download. FPGA Design with ispLEVER Tutorial 1 FPGA Design with ispLEVER Tutorial Introduction This tutorial is intended for a new user or a user who uses ispLEVER infrequently. It shows you how to use several processes, tools, and reports from the ispLEVER software suite to implement a simple (RTL) Verilog or VHDL design in a LatticeEC family device. The ispLEVER software follows an im plementation flow that generates a programming file from your CPLD design files. A similar flow exists within the Quartus II software known as the compilation flow. The compilation flow is the sequence and method by which the Quartus II.

Basic Information

• SDU Course Number: SD01331470, SD01331480
• Instructor(s): Assistant Prof Feng Li (李峰, fli@sdu.edu.cn)
• Terms offered: Fall 2016
• Level: Undergraduate
• Teaching Assistant(s): Ms Zhenjuan Qiao (乔贞娟, 1847086166@qq.com), Mr Pengfei Wang (王鹏飞, 8144756@qq.com)

Course Description

This course is to introduce the basic organization and design principles of computers. The topics include computer instructions, arithmetics, processor design, storage hierarchy, etc. Through taking this course, students will understand how a computer works and how to design a computer, from the perspectives of both hardware and software.

This course consists of two parts: lectures (SD01331470) and project design (SD01331470). The grades for SD01331470 will be based on the students' performance on assignments (20%), and final exam (80%), while the ones for SD01331470 will be given according to demos and experiment reports delivered by the students.

Remarks: This website is in construction. Related materials will be uploaded as soon as possible. If you have any problem about this website, please feel free to drop me an email.

Lecture Notes

• Computer Abstractions and Technology [PDF]
• Instructions: Language of the Computer [PDF]
• Arithmetic for Computers [PDF]
• The Processor [PDF]
• Large and Fast: Exploiting Memory Hierarchy [PDF]

• Introduction [PDF]
  We introduce the roadmap of our experiments.
• Experiment platform [PDF]
  We introduce the basic knowledge of EDA and PLD, as well as the platform of our experiments.
• Introduction to Quartus [PDF]
  We introduce the software platform of our experiments, Quartus. Please refer to Quartus II tutorial.

Experiments

Isplever Classic Tutorial

Assignments

• Assignment 1 [PDF] [Due Date: Sep 18, 2016]
• Assignment 2 [PDF] [Due Date: Oct 10, 2016]
• Assignment 3 [PDF] [Due Date: Nov 7, 2016]

Tutorials

Lattice Isplever Tutorial

• ispLEVER tutorial i (released by Latticesemi) [PDF]
• ispLEVER tutorial ii (for designing an adder) [PDF]
• Quartus II tutorial [PDF]

Useful Links

• Adder on Wiki: link
• Interesting comments: link
• CD resources of the textbook: link
• PDF version of the textbook: link
• To be added...

Isplever Classic Tutorial